ESD: Transmission line pulse (TLP) Testing

Continuing with the ESD series, one slightly advanced topic is TLP testing. When you design a product, you usually protect the device against ESD strikes. ESD strikes are given with an ESD gun(Think of it like a stun gun with a very short pulse width) going around and zapping the different parts of a product to see its immunity to ESD strikes. In a test lab, ESD strikes are usually done at points where a potential contact can happen. The problem with this test is that you get a binary pass or fail test report at the end of the test. This is OK for most devices but it doesn’t give you a clearer picture of what happened in a circuit in an ESD event. For eg, I want to understand what ESD current flow can the device can resist and which trace can handle what voltage etc. That’s where TLP testing comes into play.

In TLP testing, a high-voltage, high-current very short pulse is applied to the device under test through a transmission line. The device’s response to the TLP is then measured to determine its susceptibility to ESD damage. This is done by measuring the voltage and current on the device, as well as its ability to function correctly after the ESD event. TLP testing is a much more controlled way of getting repeatable tests done for ESD. TLP tests are usually used to generate the IV curves(which are very important) that you see in ESD protection device datasheets. The measurement setup needed for the TLP test is much more expensive than a typical ESD gun and hence you won’t find them in normal testing labs. TLP testing is done for the absolute characterisation of an ESD event.

For more info, I would suggest reading tech notes from the esdemc and sofics website.

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Back to Basics: ESD Capacitance

Last week we focussed on one facet of ESD diode selection which was unilateral vs bilateral and focussed on when to use each one of them. Another critical item to discuss is ESD capacitance. Please don’t confuse ESD Capacitance with an “ESD capacitor” which is an entirely different thing.

Every ESD diode is connected in parallel to a line/trace that it tries to protect from ESD strikes. ESD strikes are usually rare and in the normal operation of the device, ESD diodes ideally should not affect the regular functioning of the circuit. This is where the capacitance of the ESD diode matters. In normal operation, the ESD diode in the reverse biased mode, shows a capacitance due to its PN junction. The value of the capacitance has a huge role to play in the lines it protects. If you use a diode with higher capacitance to protect lets a high-speed signal like USB 3.2 Super Speed TX/RX data lanes it will create a problem. These data rates are in 10+Gbps and this pulls the line low and high at a very fast rate. Adding a larger capacitor diode will reduce its rise and fall times which will cause communication errors and you make fail the USB compliance eye diagrams.

Hence when you select an ESD diode make sure to use low-capacitance ones for high-speed data lines. You can use higher capacitance ones for GPIO/Vbus lines as there are slightly cheaper if needed. TI has a good chart(check images) on the website showing you the different capacitance ranges and which you can use for different applications based on speed.

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