The Tech Blog

There is a lot of buzz in this literal “space” about moving data centers into orbit. Space sounds cold, so it may seem like a cooling engineer’s dream. But I think this is one of the most misleading parts of the pitch.

A processor converts almost all its electrical power into heat. A 1 MW AI cluster therefore produces roughly 1 MW of waste heat. On Earth, air or water carries it to chillers, cooling towers or dry coolers. In vacuum, no surrounding fluid carries heat away. You must conduct it from the chips into cold plates and liquid loops, then spread it across radiators that emit infrared energy into space.

Radiated power follows the Stefan-Boltzmann law. It rises with radiator area and the fourth power of temp. It’s estimated that a 40 kW AI rack would need about 80 m² of radiator near 60 °C, facing deep space. At 100 MW, that becomes roughly 0.2 km². At 1 GW, it approaches 2 km², before degradation.

Now running a radiator hotter reduces its required area (though efficiency drops). But heat must flow from a hotter chip to cooler liquid and then to the radiator. Higher temperatures increase leakage, can reduce compute efficiency and shorten component life. Radiators should also face away from sunlight while solar arrays face the Sun, complicating plumbing and attitude control.

This cooling system is far from free. Radiators, pumps, pipes and coolant loops must be built, folded into a rocket, launched, deployed and protected against micrometeoroids, orbital debris, atomic oxygen and surface degradation. The same analysis estimates that coating degradation over five years could require about 40% more radiator area.

Cooling alone does not make orbital computing impossible. But it joins launch cost, radiation, high-bandwidth networking, maintenance and rapid chip obsolescence as reasons space-based AI data centers do not yet make financial sense. I can cover the other issues, with estimated numbers, in a future post. I do hope that more of this investment is directed toward R&D for more pressing problems in the world.

Earlier this week, I watched a fascinating TechTechPotato deep dive on advanced lithography. I recommend it if you have the time. Researchers have explored X-ray lithography for more than five decades, yet it has never entered mainstream chip production. Let me try throwing some light there.

Lithography transfers circuit patterns onto a light-sensitive resist on a silicon wafer. Today’s leading-edge systems use extreme ultraviolet, or EUV, light at 13.5nm. Conventional EUV optics have a numerical aperture of 0.33. High-NA EUV raises this to 0.55 and can resolve features around 8nm, but the scanner, masks and process control become harder. As features shrink further, manufacturers may again need multiple exposures for one layer. Shorter wavelengths provide another route. Moving towards 6-7nm radiation(called the Xray range) could offer finer resolution at the same numerical aperture and reduce some multi-patterning.

The trade-off starts with photon energy. A 13.5nm EUV photon carries about 92eV, while a 6.7nm photon carries about 185eV. At the same exposure dose, you therefore receive roughly half as many photons. That increases random variations in exposure, while higher-energy secondary electrons can spread through the resist and blur feature edges. The system also needs a powerful, stable source, efficient reflective optics, durable masks and near-nanometre overlay across many layers.

X-ray lithography has produced fine patterns and even functional circuits in research settings, but production tool must repeat the process across full 300mm wafers with extremely low defect density, precise overlay, high uptime and competitive throughput. Current EUV systems output around 230 wafers/hour. No commercial X-ray lithography platform currently operates in high-volume chip manufacturing. I think it remains a credible long-term frontier, but breakthroughs are still required across the board. For now, ASML’s EUV platform still remains the production benchmark.