The Tech Blog

Tech Explained: Phase Change Memory

Posted under Educational, Tech Explained on December 14th, 2025 by Amaldev

I recently read about the STM32V8 launch and it has pretty great specs. When you see that it has a 800 MHz on a Cortex-M with a 5,072 CoreMark, you know you are getting close to compute you normally see on embedded microprocessors(MPU) with an external DDR memory. ST positions STM32V8 as its flagship high-performance STM32 MCU.

The chip is built on 18nm FD-SOI plus embedded phase-change memory. FD-SOI is a chip process that reduces leakage current and helps push frequency without wasting as much power. It also integrates up to 4 MB of non-volatile memory and is specified up to an extreme 140°C junction temperature. The key part is the PCM.

Embedded phase-change memory (PCM) is a way to store bits without the floating gate used in Flash. The bit lives as resistance in a special material. When the material is in one phase it reads high resistance, and in the other phase it reads low resistance. Because the phase stays put when power is removed, it is non-volatile memory. You write to it by sending a short, shaped current pulse that heats the cell into the wanted phase.

This matters because embedded Flash does not scale nicely into newer chip process nodes. Resistive memories like PCM is the route most vendors take from around 28nm and below, mainly to avoid extra process complexity and cost. RRAM was another, I wrote about that one earlier in a post.

For firmware, PCM is not an infinite-write storage. The chip separates code and data profiles. Code can be around 1,000 write cycles with 10-year retention. Data can be up to 1,00,000 cycles with about 1-year retention at 140°C after cycling. This is actually great as realistically you wont have firmware changes that frequent in production. The practical benefit is you can keep more code, tables, and even small ML model weights on chip, and then buffer hot data in SRAM, the fast RAM that forgets its contents when power is off.

The new V8 chip seems to be in sampling mode currently by ST with elite customers like SpaceX because of the temp profile and radiation immunity claims.

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Back to Basics: Rail to Rail Opamps

Posted under Back to Basics, Educational on December 7th, 2025 by Amaldev

Today we discuss one of the most basic characteristic of an opamp.

Rail to Rail opamp purely means an opamp whose input and output stages are designed to operate with signal voltages that are very close to both power supply rails under specified conditions. Meaning on a ±5V supply a rail to rail opamp might accept inputs from about −4.9V to +4.9V and drive outputs from about −4.95V to +4.95V into a light load, instead of being limited to something like−4.3V to 4.7V like a non-rail-to-rail opamp.

The key spec behind this is the common-mode input voltage(the voltage that is sitting on both inputs) range. If the datasheet says Vcm = V− to V+ + 0.1V, the input really reaches both rails (and a bit beyond). If it instead says Vcm = V− to V+ − 1.2V on ±5V, the input is valid from −5V to only +3.8V, so it is rail to negative rail, not truly rail to rail. Whenever you pick an opamp, this single line tells you how close your real circuit can get to each rail.

You also need to watch the output swing. The datasheet tells you how close the output can get to each rail at a given load. Into 10kΩ it may sit a few tens of millivolts away. Into 1kΩ that gap can jump to a few hundred millivolts.

The rule of thumb I try to follow is to keep signals at least 0.1V inside each rail, unless the graphs clearly prove better. On a 3.3V front end, I budget 0.1V to 3.2V as the working range and treat anything closer as margin.

When you pick a device, filter by supply and package, then read the common mode range and the output swing at your load. Only after that, think about offset and noise. This habit avoids parts that look fine, but quietly clip the last few millivolts.

A mostly unknown fact is that many rail to rail input opamps use two input pairs that hand over near mid-supply, so their worst distortion often appears around mid-scale instead of at the rails.

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